1. Technical Field
The present invention relates to a signal processing device which analog-to-digital converts data recorded on an information recording medium to reproduce the data. More particularly, the invention relates to an improvement of a technique for adjusting a DC voltage of an analog signal in order to efficiently use an input dynamic range of an A/D converter.
2. Background Art
While an analog signal processing IC and a digital signal processing LSI have conventionally been configured in different chips, approaches for reducing circuit scale, footprint, and external parts by integrating these ICs in one chip have been made. Further, a cost-down effect due to semiconductor process shrinkage can be easily obtained by promoting digitization of analog signal processing circuits.
With these approaches, the conventional signal processing circuit is required to perform efficient analog-to-digital conversion in a unit for converting an analog signal into a digital signal (hereinafter referred to as A/D conversion), that is, to covert an analog signal into a digital signal with the maximum amplitude, within an input dynamic range of an A/D converter.
As an example of such conventional art, one disclosed in Patent Document 1 has been known.
FIG. 2 shows the conventional signal processing device disclosed in Patent Document 1, which is arbitrarily modified to facilitate the explanation.
The conventional signal processing device comprises, for example, a high-pass filter 8 which cuts off a low-frequency component included in an input signal that is reproduced from an information recording medium to remove a DC offset from the reproduced signal, a variable gain amplifier 9 which gives a gain according to an input gain control signal to the reproduced signal from which the DC offset has been removed by the high-pass filter 8, an equalizer 10 which receives an output of the variable gain amplifier 9 and performs waveform equalization, an offset unit 11 which receives an output of the equalizer 10 and gives a DC offset according to an input offset control signal to the input signal, an A/D converter 3 which receives an output of the offset unit 11 and performs analog-to-digital conversion, a peak detector 4 which performs peak detection from sampling data obtained by the A/D converter 3, a bottom detector 5 which performs bottom detection from the sampling data obtained by the A/D converter 3, an amplitude detector 12 which calculates amplitude information in the input signal to the A/D converter 3 from the detected peak value and the detected bottom value, an offset detector 6 which calculates offset information in the input signal to the A/D converter 3 from the detected peak value and the detected bottom value, a gain controller 14 which controls the variable gain amplifier 9 to make the input amplitude of the A/D converter 3 constant, based on the amplitude information obtained by the amplitude detector 12, and an offset controller 13 which controls the offset unit 11 to make the input offset of the A/D converter 3 constant, based on the offset information obtained by the offset detector 6.
Next, the operation will be described. For example, a signal recorded in an information recording medium such as an optical disc is reproduced by a reproduction means such as an optical pickup. A low-frequency component is removed from the reproduced by the high-pass filter 8, and the resultant signal is output to the variable gain amplifier 9.
The variable gain amplifier 9 is controlled to make the input amplitude of the A/D converter 3 constant, and gives the controlled gain to the input signal from the high-pass filter 8. The equalizer 10 performs equalization to the output signal from the variable gain amplifier 9.
The offset unit 11 is controlled to make the input offset of the A/D converter 3 constant, and gives the controlled offset to the input signal from the equalizer 10.
The A/D converter 3 converts the output signal of the offset unit 11 from an analog signal to a digital signal. The peak detector 4 detects a peak of the output signal from the A/D converter 3, and the bottom detector 5 detects a bottom of the output signal from the A/D converter 3.
The amplitude detector 12 calculates amplitude information of the input signal to the A/D converter 3 from the signals detected by the peak detector 4 and the bottom detector 5, thereby to detect the amplitude information. The gain controller 14 controls the gain to be given by the variable gain amplifier 9 so as to make the input amplitude of the A/D converter 3 constant, based on the amplitude information detected by the amplitude detector 12.
The offset detector 6 calculates offset information of the input signal to the A/D converter 3 from the signals detected by the peak detector 4 and the bottom detector 5, thereby to detect the offset information. The offset controller 13 controls the offset to be given by the offset controller 13 so as to make the input offset of the A/D converter 3 constant, based on the offset information detected by the offset detector 6.
The function of the equalizer 10 will be described in more detail. When reproducing a high-density recorded optical medium or the like, the signal amplitudes of relatively short recording marks are reduced due to optical frequency characteristics. Therefore, the equalizer 10 boosts up this frequency band to improve the SNR (Signal to Noise Ratio) of the signal.
Next, the function of the offset unit 11 will be described in more detail. Although the input signal to the high-pass filter 8 becomes DC free after passing through the high-pass filter 8, if the recording marks are formed larger or smaller than their proper lengths due to variations in the manufacturing stage of the information recording medium, the ratio between the “H” section and “L” section of the signal deviates from 50:50, and this deviation causes a phenomenon that the average DC level of the reproduced signal deviates from the center position between the upper and lower peaks of the reproduced signal. This phenomenon frequently occurs when the recording condition is not appropriate, and it is generally called “asymmetry”.
When the reproduced signal having such asymmetry passes through the high-pass filter 8, its DC component is cut off, and a DC offset occurs in the input signal to the A/D converter 3 as shown in FIG. 3. As the DC offset increases, the reproduced signal waveform might exceed the input dynamic range of the A/D converter 3, which causes a problem that a portion of the waveform is lost and thereby correct A/D conversion cannot be performed. In the conventional configuration shown in FIG. 2, the offset unit 11 is placed behind the high-pass filter 8 to provide a control loop for controlling the offset unit 11 by the offset controller 13. Thereby, even when a reproduced signal having an asymmetry is inputted, this reproduced signal can be efficiently included in the input dynamic range of the A/D converter 3.
Next, a format of a DVD-RAM which is a kind of an optical disc will be described.
As a physical format of the DVD-RAM, a wobble land/groove system is adopted. The wobble land/groove system is, as shown in FIG. 4, a system of recording marks in a convex groove track 15 and a concave land track 16 which are recorded on the surface of the optical disc, viewed from the side to which laser light is applied.
The groove track 15 and the land track 16 are separated into units called sectors, and a header region 17 is formed at the beginning of each sector. In this header region 17, sector address information has been recorded in the form of a pit sequence at the time of manufacture. Therefore, in the wobble land/groove system, detection of the sector address can be performed by reading the pit sequence in the header region 17.
In the header region 17, the pit sequence is divided into two parts in the track direction, and the respective pit sequences are arranged in the form called CAPA (Complementary Allocated Pit Address), i.e., arranged so as to be offset at an interval that is half the track width (pitch), alternately in the radial direction of the optical disc, with respect to the respective tracks.
By the way, as a conventional art for reproducing a information recording medium having a format such as the DVD-RAM format, one disclosed in Patent Document 2 has been known.
FIG. 5 shows a front-end part of a conventional optical disc reproducing apparatus disclosed in Patent Document 2. To be specific, reading of recorded data from an optical disc 18 is performed by an optical disc 20 with the optical disc 18 being rotated by a spindle motor 19. Initially, in the optical head 20, laser light emitted from a laser diode 20a travels straight through a beam splitter 20b to be applied onto the recording surface of the optical disc 18 via an objective lens 20c. When the laser light reflected from the optical disc 18 travels backward to reach the beam splitter 20b via the objective lens 20c, it is reflected by the beam splitter 20b at about a right angle to the advancing direction to be received by a photodetector 20d. 
The light-receiving area of the photodetector 20d is divided into two parts along each of the radial direction and the tangential direction with respect to the track sequence on the optical disc 18, i.e., it is divided into four light-receiving areas. Electrical signals obtained from the four light-receiving areas of the photodetector 20d are converted from current signals into voltage signals by I/V conversion amplifiers 21a, 21b, 21c, and 21d, respectively, and then level-added by an adder 22 to produce a sum signal.
In this sum signal, as shown in FIG. 6(b), the DC level obtained in the header field 17 is higher than the DC level obtained in the data field.
The reason why the DC level of the sum signal in the data field is low is because there is a difference in height between the groove track 15 and the land track 16, and when the reflected lights from the both tracks are mixed, the lights having different phases to the wavelength interfere with each other to weaken each other.
Therefore, in the optical disc device, the sum signal outputted from the adder 22 is passed through the high-pass filter 8 to cut off the DC component in the sum signal, thereby to absorb the difference in the DC level between the header region 17 and the data region 23. The sum signal from which the DC level difference has been removed by the high-pass filter 8 is input to the variable gain amplifier 9 shown in FIG. 2.
By the way, the time constant of the operation of the high-pass filter 8 must be set short in order to rapidly absorb the DC level of the sum signal, at the timing when the DC level of the sum signal is changed, i.e., at the timing when the sum signal in the data region is changed to that in the header region or when the sum signal in the header region is changed to that in the data region.
On the other hand, when the time constant of the operation of the high-pass filter 8 is set short, there may occur a drawback that the low-frequency component of the input data has a distortion.
Therefore, in the optical disc device, the sum signal is supplied to a pull-in pulse generation circuit 24 shown in FIG. 5, and as shown in FIG. 6(b), a pull-in pulse which becomes H level for a predetermined period is generated at the timing when the DC level of the sum signal is changed to be supplied to the high-pass filter 8. The high-pass filter 8 is switched between the state where the time constant of its operation is short and the state where it is long, for the H level section and the L level section of the pull-in pulse, respectively.
Thereby, as shown in FIG. 6(c), the high-pass filter 8 can rapidly pull the sum signal after the DC level change into the state where the DC level is cut off, and can prevent the pulled-in sum signal from having a distortion.
A configuration example of the high-pass filter 8 is shown in FIG. 7.
The high-pass filter 8 has capacitors 28 and 29 between an LSI terminal 25 and LSI terminals 26 and 27, respectively, and thus the high-pass filter 80 is configured by the capacitor 28 or the capacitor 29 and a resistor 30 inside the LSI. Selection of the capacitor 28 or 29 to be connected is performed by providing analog switches 31 and 32 in the LSI, and switching the capacitors 28 and 29 according to a control signal from the pull-in pulse generator 24 so that one of the capacitors is turned on while the other is turned off.
The required cutoff frequency of the high-pass filter 8 is several tens Hz in the data region, and it must be set at several hundreds kHz in order to absorb a DC difference in the header region, and therefore, it is necessary to switch the cutoff frequency in the order of about 10000 times.
As another method of switching the cutoff frequency, switching of the resistance value can be considered. However, when using the resistor in the LSI, it is difficult to accurately produce a pair of resistors having a resistance value of about 10000 times. Further, since it is also difficult to produce a pair of capacitors having a capacitance value of 10000 times, it is necessary to adopt a configuration which enables switching of the capacitance value using a capacitor externally attached to the LSI as shown in FIG. 7, or a configuration which enables switching of the resistance value using an external resistor.    Patent Document 1: International Publication No. 03/077248    Patent Document 2: Japanese Published Patent Application No. 2000-182239
FIG. 8 is a graph illustrating the relation between the semiconductor process rule and the ratio of the pad area to the chip area. A pad is an electrode onto which a wire 33 is bonded when a terminal of an LSI is connected to a lead frame by the wire. As shown in FIG. 9, an end of a lead frame 34 is a portion to be a terminal of the LSI, and an electrode existing on the periphery of a semiconductor chip 35 is a pad 36. The LSI is completed by sealing the external surface of the LSI with a resin, and then cutting the terminal portions.
As shown in FIG. 8, when semiconductor chips of the same circuit scale are assumed, the areas of pads in the chips must be equal to each other regardless of the process rule. Accordingly, when the chips are equipped with circuits of the same function, the ratio of the pad area to the chip area is increased as the process rule is decreased, resulting in a disadvantage costwise.
FIG. 10 is a rough schematic diagram of the chip. In FIG. 10, reference numeral 37 denotes an actual circuit part, and reference numeral 36 denotes pads.
In FIG. 10, the semiconductor chip size depends on the number of pads, and the effect of process shrinkage cannot be exerted. That is, when shrinkage of the semiconductor process rule is further advanced hereafter, a reduction in the number of terminals will be an important challenge.
By the way, as shown in FIG. 7, the conventional high-pass filter 8 for absorbing a difference in DC voltage in the input signal requires three terminals.
Further, when the reproduced signal is transferred by a differential transfer method to improve the S/N characteristics, six terminals are required in the conventional art, and the number of terminals will be further increased.
The present invention is made to solve the above-described problems and has for its object to provide a signal processing device which can absorb a difference in DC component between reproduced signals in different reproduction sections by effectively performing an offset control, without using the method of switching the time constant of a high-pass filter to absorb a steep DC difference.